1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
Due to progress in semiconductor technology, particularly in fine processing technology, the downsizing and increased capacitance of transistors and memory cells have rapidly advanced. For example, a device (hereinafter referred to a “vertical transistor”) has been proposed which includes a transistor or memory cell using the side wall of a columnar semiconductor formed on a substrate. In the vertical transistor, the length direction of a gate of the transistor or memory cell agrees with the height direction thereof, so there is no occurrence of short-channel effects. Further, when elements are stacked in the height direction, high density can be implemented without increasing the area; thus it is use of the vertical transistor as an approach for implementing cost reduction and increased capacitance of a semiconductor device can be expected. Further, the vertical transistor has excellent features such that it is relatively easy to form an element of a partial depletion type structure or a perfect depletion type structure and such that a high-speed device or an element that consumes of lower power consumption can be formed using a field concentration effect. It has also been proposed that a DRAM (Dynamic Random Access Memory) with a memory cell having a unit memory cell size of 4 F2 (F being a design rule) be constructed using such a vertical transistor. In the 4 F2 type memory cell, a cross-point type layout is typically used in which a vertical transistor is arranged at the intersection of a word line and a bit line (refer to Japanese patent application Laid-Open Nos. 2007-329480 and 2002-026279).
Japanese patent application Laid-Open No. 2003-209187 discloses a layout in which bit lines are bent 30 degrees for each cell by utilizing a vertical transistor. In the layout in which bit lines are bent for each cell, patterning by lithography is extremely difficult to implement, compared to a layout in which bit lines are linear. Consequently, both the word line and bit line are preferably linear.
Meanwhile, electrical charges held in a DRAM capacitor disappear in the course of nature due to leak current. When electrical charges totally disappear, the data held in the capacitor cannot be retrieved. Thus, before electrical charges totally disappear, there is a need to rewrite electrical charges. Consequently, as the quantity of electrical charges capable of being accumulated in the capacitor increases, the number of rewrite times becomes smaller, allowing reduction of power consumption of DRAM. Accordingly, the capacitor capacitance of DRAM is preferably greater.
FIG. 1 is a plan view schematically illustrating arrangement of a word line, bit line and capacitor in a related art cross-point type memory cell. Referring to FIG. 1, circular capacitor 3 is arranged at the intersection of word line 1 and bit line 2. Word line 1 is patterned so that the line pitch equivalent to the sum of the width and the interval is Wa. Bit line 2 is patterned so that the line pitch equivalent to the sum of the width and the interval is Ba. Word line 1 is regularly arranged in a Y direction at a line pitch of Wa. Bit line 2 is regularly arranged in an X direction at a line pitch of Ba. When F denotes a minimum processing size (design rule) in manufacturing, word line pitch Wa and bit line pitch Ba are expressed as follows.Word line pitch Wa=2×F Bit line pitch Ba=2×F 
That is, the word lines and bit lines are arranged so that the line pitches thereof are equal to each other.
In the case of a circular capacitor such as a cylinder type or pillar type capacitor, when the diameter (inside diameter) of the capacitor is R and the height thereof is H, capacitor capacitance C′ is proportional to the product of the diameter and the height (C′=R×H). Referring to FIG. 1, when the space between the adjacent capacitors is S, capacitor diameter R is equal to 2×F−S(R=2×F−S). As device miniaturization progresses, the minimum processing size (F) becomes smaller, so the capacitor diameter (R) also becomes smaller and the capacitor capacitance decreases. Consequently, the number of times of refresh operations (rewrite operations) increases, so the power consumption of DRAM becomes greater.